Verified Job
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Verification Manager
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#493370
Full Time
Job Description
J
JPMorgan Chase
SoftwareEngineerIIIDataEngineering
JPMorgan Chase • बेंगलुरु, Karnataka • Hispanic Alliance For Career Enhancement के ज़रिए
14 दिन पहले
फ़ुल-टाइम
आवेदन करें: Hispanic Alliance For Career Enhancement
काम का वर्णन
There's nothing more exciting than being at the center of a rapidly growing field in technology and applying your skillsets to drive innovation and modernize the world's most complex and mission-critical systems.
As a Site Reliability Engineer III at JPMorgan Chase within the Corporate Technology, you will solve complex and broad business problems with simple and straightforward solutions. Throug...
इस लिस्टिंग की शिकायत करें
Mulya Technologies
Verification Manager
Mulya Technologies • अनंतपुर, Andhra Pradesh • Talent.com के ज़रिए
23 दिन पहले
फ़ुल-टाइम
किसी डिग्री का ज़िक्र नहीं है
आवेदन करें: Talent.com
आवेदन करें: Jobrapido.com
काम का वर्णन
www.Sevyamultimedia.com
Verification Design Manager / Lead
About Us
We are a technology consulting company delivering best-in class Chip Design Services.
Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.
With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills
Our embedded design services are centered around FW validation & Test Automation
Chip Design Services
Analog IP Design
Foundation - OpAmp, Bandgap
IOs - GPIO, I2C, LVDS
Clocking - PLL
Power - LDO
SoC Design
RTL Design, Integration, Lint / CDC / RDC, UPF
IP / SoC UVM Verification
PPA, Synthesis, Constraints Management
Physical Design, Timing Closure, ECOs
Sign-off - Timing, Power, EM / IR, DRC / LVS / ERC
PDK, Design Automation
DRC / LVS / Extraction Rule deck Development
PCell Development
Automation Tools in Perl, Python, GoLang
Approach
We support a mix of engagement models to support diverse client requirements.
Engagement Models
Turnkey (SoW) Engagement
Staff Augmentation (T&M)
Offshore Design Center
Key Enablers
Hands on Leadership
Proven Industry Experts
TSMC DCA Parternship
Collaboration with Academia
Design Verification Manager / Lead
Job Description : Design Verification Manager / Lead
DV lead / manager to verify IP / SoC using System Verilog / UVM
Exposure to various interface IP like I2C / SPI / UART / USB / NVM / PCIe; Buses AXI / AHB / APB; ARM based SoC designs is needed.
Skills :
• Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog / C / UVM.
• Generic knowhow on Digital Design and Verification methodologies.
• Experience in System Verilog / UVM based IP / SoC verification using advanced technologies.
• Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement
• Proficient in EDA tools used for Design Verification (e.g. Cadence / Mentor / Synopsys simulation suites; Verilator).
• Working knowledge of Unix, Linux and SKILL, Shell / Python Script ability.
• Quick learner with excellent interpersonal, verbal / written communications, problem solving and decision-making skills
Traits :
• Adaptable, Flexible, Global Approach / Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
• Solutions orientation; Quality driven; Execution minded
Contact : Uday
Mulya Technologies
muday_bhaskar@yahoo.com
Mining The Knowledge Community"
JPMorgan Chase
SoftwareEngineerIIIDataEngineering
JPMorgan Chase • बेंगलुरु, Karnataka • Hispanic Alliance For Career Enhancement के ज़रिए
14 दिन पहले
फ़ुल-टाइम
आवेदन करें: Hispanic Alliance For Career Enhancement
काम का वर्णन
There's nothing more exciting than being at the center of a rapidly growing field in technology and applying your skillsets to drive innovation and modernize the world's most complex and mission-critical systems.
As a Site Reliability Engineer III at JPMorgan Chase within the Corporate Technology, you will solve complex and broad business problems with simple and straightforward solutions. Throug...
इस लिस्टिंग की शिकायत करें
Mulya Technologies
Verification Manager
Mulya Technologies • अनंतपुर, Andhra Pradesh • Talent.com के ज़रिए
23 दिन पहले
फ़ुल-टाइम
किसी डिग्री का ज़िक्र नहीं है
आवेदन करें: Talent.com
आवेदन करें: Jobrapido.com
काम का वर्णन
www.Sevyamultimedia.com
Verification Design Manager / Lead
About Us
We are a technology consulting company delivering best-in class Chip Design Services.
Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.
With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills
Our embedded design services are centered around FW validation & Test Automation
Chip Design Services
Analog IP Design
Foundation - OpAmp, Bandgap
IOs - GPIO, I2C, LVDS
Clocking - PLL
Power - LDO
SoC Design
RTL Design, Integration, Lint / CDC / RDC, UPF
IP / SoC UVM Verification
PPA, Synthesis, Constraints Management
Physical Design, Timing Closure, ECOs
Sign-off - Timing, Power, EM / IR, DRC / LVS / ERC
PDK, Design Automation
DRC / LVS / Extraction Rule deck Development
PCell Development
Automation Tools in Perl, Python, GoLang
Approach
We support a mix of engagement models to support diverse client requirements.
Engagement Models
Turnkey (SoW) Engagement
Staff Augmentation (T&M)
Offshore Design Center
Key Enablers
Hands on Leadership
Proven Industry Experts
TSMC DCA Parternship
Collaboration with Academia
Design Verification Manager / Lead
Job Description : Design Verification Manager / Lead
DV lead / manager to verify IP / SoC using System Verilog / UVM
Exposure to various interface IP like I2C / SPI / UART / USB / NVM / PCIe; Buses AXI / AHB / APB; ARM based SoC designs is needed.
Skills :
• Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog / C / UVM.
• Generic knowhow on Digital Design and Verification methodologies.
• Experience in System Verilog / UVM based IP / SoC verification using advanced technologies.
• Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement
• Proficient in EDA tools used for Design Verification (e.g. Cadence / Mentor / Synopsys simulation suites; Verilator).
• Working knowledge of Unix, Linux and SKILL, Shell / Python Script ability.
• Quick learner with excellent interpersonal, verbal / written communications, problem solving and decision-making skills
Traits :
• Adaptable, Flexible, Global Approach / Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
• Solutions orientation; Quality driven; Execution minded
Contact : Uday
Mulya Technologies
muday_bhaskar@yahoo.com
Mining The Knowledge Community"
