Verified Job
Engineering - Architecture
STA(PD) Engineer - 5+ Years(EXP)
Engineering - Architecture
#778537
Remote / WFH
AIonSi
Job Description
Company Description AIonSi is a semiconductor solutions startup delivering VLSI design and verification, automotive functional safety, and artificial intelligence services to clients across the global semiconductor industry. Led by a team of seven industry experts, the company focuses on providing end-to-end solutions for complex SoC designs and assumes full ownership from concept to implementation. AIonSi positions itself as a one-stop platform for IP and SoC design, integration, verification, gate-level simulation (GLS), and physical design. The organization emphasizes best-in-class service with a strong commitment to quality, making it an environment suited for professionals who value technical excellence and comprehensive project involvement.
Role Description The STA (Physical Design) Engineer role at AIonSi is a full-time, on-site position based in Bengaluru South. The engineer will be responsible for performing static timing analysis for complex SoC and IP designs, collaborating closely with physical design, front-end, and verification teams to ensure timing closure across multiple process corners and operating conditions. Day-to-day tasks include setting up STA environments, developing and validating timing constraints, analyzing reports, identifying violations, and driving fixes in coordination with implementation engineers. The role also involves working on sign-off timing, supporting ECOs, optimizing performance, power, and area, and ensuring that all timing-related deliverables meet quality and schedule targets. The engineer will contribute to methodology improvements and best practices to strengthen AIonSi’s physical design and STA capabilities.
Qualifications
• Candidates should possess strong expertise in static timing analysis tools and flows (e.g., PrimeTime or equivalent), including constraint development, timing closure, and sign-off methodologies.
• Candidates should possess solid physical design knowledge, such as floorplanning, placement, clock tree synthesis, routing, and ECO implementation in advanced technology nodes.
• Candidates should possess familiarity with RTL-to-GDSII flows, synthesis, and interaction between front-end and back-end teams to resolve timing and implementation issues.
• Candidates should possess proficiency in scripting and automation (e.g., Tcl, Python, Shell) to analyze STA results, build utilities, and improve efficiency.
• Candidates should possess understanding of signal integrity, power, noise, and variation impacts on timing, along with experience working across different PVT corners.
• Candidates should possess strong analytical and problem-solving skills, with the ability to debug complex timing and design issues under schedule constraints.
• Candidates should possess effective communication and collaboration skills to work with cross-functional teams and document methodologies and results clearly.
• Beneficial qualifications include 5+ years of relevant experience in STA/PD, exposure to complex SoC designs, experience in automotive or safety-critical domains, and a degree in Electrical/Electronics Engineering
Location : Bangalore / Hyderabad
Experience : 5+ Years
Preference : Immediate joiners
Role Description The STA (Physical Design) Engineer role at AIonSi is a full-time, on-site position based in Bengaluru South. The engineer will be responsible for performing static timing analysis for complex SoC and IP designs, collaborating closely with physical design, front-end, and verification teams to ensure timing closure across multiple process corners and operating conditions. Day-to-day tasks include setting up STA environments, developing and validating timing constraints, analyzing reports, identifying violations, and driving fixes in coordination with implementation engineers. The role also involves working on sign-off timing, supporting ECOs, optimizing performance, power, and area, and ensuring that all timing-related deliverables meet quality and schedule targets. The engineer will contribute to methodology improvements and best practices to strengthen AIonSi’s physical design and STA capabilities.
Qualifications
• Candidates should possess strong expertise in static timing analysis tools and flows (e.g., PrimeTime or equivalent), including constraint development, timing closure, and sign-off methodologies.
• Candidates should possess solid physical design knowledge, such as floorplanning, placement, clock tree synthesis, routing, and ECO implementation in advanced technology nodes.
• Candidates should possess familiarity with RTL-to-GDSII flows, synthesis, and interaction between front-end and back-end teams to resolve timing and implementation issues.
• Candidates should possess proficiency in scripting and automation (e.g., Tcl, Python, Shell) to analyze STA results, build utilities, and improve efficiency.
• Candidates should possess understanding of signal integrity, power, noise, and variation impacts on timing, along with experience working across different PVT corners.
• Candidates should possess strong analytical and problem-solving skills, with the ability to debug complex timing and design issues under schedule constraints.
• Candidates should possess effective communication and collaboration skills to work with cross-functional teams and document methodologies and results clearly.
• Beneficial qualifications include 5+ years of relevant experience in STA/PD, exposure to complex SoC designs, experience in automotive or safety-critical domains, and a degree in Electrical/Electronics Engineering
Location : Bangalore / Hyderabad
Experience : 5+ Years
Preference : Immediate joiners
