πΉ Lead the design and optimization of high-performance, low-power standard cells for advanced process nodes with a strong focus on PPA (Power, Performance & Area).
πΉ Design sequential and combinational standard cells and arithmetic building blocks at the transistor level.
πΉ Develop schematics using Cadence Virtuoso.
πΉ Perform post-layout validation, PVT and Monte Carlo verification, and reliability sign-off.
πΉ Apply low-power design methodologies and collaborate with Layout, Characterization, STA, CAD, and Product Engineering teams to deliver silicon-ready libraries.
πΉ Drive design methodology improvements and mentor engineering teams.