Verified Job
Hardware / Network Engineer
Principal Design for Test (DFT) Engineer /Senior DFT Engineer(Mid to Senior Level)
Hardware / Network Engineer
#776665
Remote / WFH
Mulya Technologies
Job Description
Role Overview
We are looking for a hands-on DFT engineer to implement and execute the full test flow on our complex, high-performance AI/Networking SoCs. This is an execution role: you will insert and verify DFT logic, run compression and ATPG, close coverage and DFT timing, and take patterns through gate-level simulation to ATE bring-up and silicon debug.
Key Responsibilities
• Scan Insertion & Compression: Implement scan-chain insertion, stitching, and reordering, and run EDT/compression to hit coverage and pattern-count targets.
• MBIST & IJTAG Integration: Integrate and bring up memory BIST and repair, IEEE 1687 (IJTAG) networks, JTAG, and boundary scan.
• ATPG Execution: Run ATPG (stuck-at, transition-delay, cell-aware), debug low-coverage areas, and drive coverage to sign-off targets.
• Pattern Simulation & Verification: Run gate-level simulations (GLS), debug pattern mismatches, and generate test protocols and patterns.
• DFT Timing Closure: Work hands-on with Physical Design to close timing on scan and test-mode paths.
• ATE Bring-up & Silicon Debug: Convert patterns to ATE format, support post-silicon bring-up, and debug failures on the tester.
• DFT Integration & Verification: Insert and verify DFT structures (EDT, compression, hierarchical DFT) and ensure test-friendly RTL/netlist.
• Test Cost: Optimize test time and pattern volume to reduce overall test cost.
Key Skills
• DFT Domain Expertise: Expert-level, hands-on knowledge of Mentor Tessent (TK/IJTAG).
• Comprehensive Test Coverage: Deep, hands-on experience in Scan Compression, MBIST, Hierarchical DFT, and IEEE 1687 (IJTAG) standards.
• Design & Timing: Solid understanding of RTL design (Verilog/SystemVerilog) and the impact of DFT on Static Timing Analysis (STA).
• Scripting & Automation: Highly proficient in Tcl, Perl, or Python to automate complex DFT flows and pattern processing.
• Advanced Methodologies: Experience with BIST for High-Speed SerDes, HBM (High Bandwidth Memory), and thermal/power-aware testing for large-scale AI chips.
• Debug & Diagnosis: Strong hands-on experience in gate-level simulations (GLS) and silicon debug on the tester.
Preferred Qualifications
• Academic Background: Bachelor’s or Master’s in Electrical/Electronics Engineering or a related field.
• Hands-on DFT Scope: Experience implementing DFT for multi-die or Chiplet-based designs.
• AI/High-Tech Exposure: Familiarity with high-power AI accelerators and their test challenges (e.g., massive gate counts, power-hungry scan).
• Startup Mindset: Proven ability to build and run flows from scratch and thrive in a fast-paced, high-execution environment.
We are looking for a hands-on DFT engineer to implement and execute the full test flow on our complex, high-performance AI/Networking SoCs. This is an execution role: you will insert and verify DFT logic, run compression and ATPG, close coverage and DFT timing, and take patterns through gate-level simulation to ATE bring-up and silicon debug.
Key Responsibilities
• Scan Insertion & Compression: Implement scan-chain insertion, stitching, and reordering, and run EDT/compression to hit coverage and pattern-count targets.
• MBIST & IJTAG Integration: Integrate and bring up memory BIST and repair, IEEE 1687 (IJTAG) networks, JTAG, and boundary scan.
• ATPG Execution: Run ATPG (stuck-at, transition-delay, cell-aware), debug low-coverage areas, and drive coverage to sign-off targets.
• Pattern Simulation & Verification: Run gate-level simulations (GLS), debug pattern mismatches, and generate test protocols and patterns.
• DFT Timing Closure: Work hands-on with Physical Design to close timing on scan and test-mode paths.
• ATE Bring-up & Silicon Debug: Convert patterns to ATE format, support post-silicon bring-up, and debug failures on the tester.
• DFT Integration & Verification: Insert and verify DFT structures (EDT, compression, hierarchical DFT) and ensure test-friendly RTL/netlist.
• Test Cost: Optimize test time and pattern volume to reduce overall test cost.
Key Skills
• DFT Domain Expertise: Expert-level, hands-on knowledge of Mentor Tessent (TK/IJTAG).
• Comprehensive Test Coverage: Deep, hands-on experience in Scan Compression, MBIST, Hierarchical DFT, and IEEE 1687 (IJTAG) standards.
• Design & Timing: Solid understanding of RTL design (Verilog/SystemVerilog) and the impact of DFT on Static Timing Analysis (STA).
• Scripting & Automation: Highly proficient in Tcl, Perl, or Python to automate complex DFT flows and pattern processing.
• Advanced Methodologies: Experience with BIST for High-Speed SerDes, HBM (High Bandwidth Memory), and thermal/power-aware testing for large-scale AI chips.
• Debug & Diagnosis: Strong hands-on experience in gate-level simulations (GLS) and silicon debug on the tester.
Preferred Qualifications
• Academic Background: Bachelor’s or Master’s in Electrical/Electronics Engineering or a related field.
• Hands-on DFT Scope: Experience implementing DFT for multi-die or Chiplet-based designs.
• AI/High-Tech Exposure: Familiarity with high-power AI accelerators and their test challenges (e.g., massive gate counts, power-hungry scan).
• Startup Mindset: Proven ability to build and run flows from scratch and thrive in a fast-paced, high-execution environment.
