Verified Job
Engineering - Architecture
Staff Engineer Analog Design- Serdes
Engineering - Architecture
#50763
Remote / WFH
Synopsys
Job Description
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in the trenches of analog design, working on circuits that move data at speeds most people cannot fathom. SerDes is not just a buzzword to you, it is the domain where you have built voltage-mode drivers, tuned PLLs until they locked cleanly, and debugged equalization schemes that looked perfect in simulation but needed three more iterations in layout. You know that a well-designed CDR is the difference between a link that works and one that fails margin at the customer site.
What You'll Be Doing
• Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators
• Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications
• Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes
• Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune your analog circuits in real time
• Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions
• Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products
• Own the full lifecycle of your blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD
The Impact You Will Have
• Your circuits will enable multi-gigabit data transfer in AI accelerators, data center switches, automotive SoCs, and consumer electronics shipping in millions of units
• You will help Synopsys deliver SerDes IP that meets the performance and power targets our customers depend on to win in competitive markets
• Your layout optimization and simulation rigor will reduce respins, saving months of schedule and significant engineering cost
• The verification strategies you define will catch corner-case failures before tapeout, improving first-pass silicon success rates
• Your collaboration with digital and system teams will ensure analog-digital co-design works seamlessly, not just in theory but in real integrated test chips
• You will contribute to the technical foundation of next-generation high-speed standards, influencing how the industry builds faster, more efficient links
• Your documentation and knowledge sharing will raise the design quality and speed of the entire analog team
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in the trenches of analog design, working on circuits that move data at speeds most people cannot fathom. SerDes is not just a buzzword to you, it is the domain where you have built voltage-mode drivers, tuned PLLs until they locked cleanly, and debugged equalization schemes that looked perfect in simulation but needed three more iterations in layout. You know that a well-designed CDR is the difference between a link that works and one that fails margin at the customer site.
What You'll Be Doing
• Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators
• Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications
• Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes
• Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune your analog circuits in real time
• Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions
• Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products
• Own the full lifecycle of your blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD
The Impact You Will Have
• Your circuits will enable multi-gigabit data transfer in AI accelerators, data center switches, automotive SoCs, and consumer electronics shipping in millions of units
• You will help Synopsys deliver SerDes IP that meets the performance and power targets our customers depend on to win in competitive markets
• Your layout optimization and simulation rigor will reduce respins, saving months of schedule and significant engineering cost
• The verification strategies you define will catch corner-case failures before tapeout, improving first-pass silicon success rates
• Your collaboration with digital and system teams will ensure analog-digital co-design works seamlessly, not just in theory but in real integrated test chips
• You will contribute to the technical foundation of next-generation high-speed standards, influencing how the industry builds faster, more efficient links
• Your documentation and knowledge sharing will raise the design quality and speed of the entire analog team
