Verified Job
Engineering - Architecture
Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture)
Engineering - Architecture
#743578
Remote / WFH
Synopsys · Bengaluru, Karnataka ·
Job Description
Job description
Job Title:
• Principal Digital Design Engineer, PCIe
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years deep in the details of PCIe digital design, and somewhere along the way you became the person others come to when a design decision matters or when something complex needs untangling. You know PCIe architecture not just from specs but from living through silicon bring-up, debugging corner cases at 2 a.m., and watching designs either hold up or fall apart under real-world conditions. That experience shaped how you think about micro-architecture, trade-offs, and what actually ships.
You are technical first. You still review RTL. You still care about how a clock domain crossing is handled or whether a state machine will scale to the next generation. But you have also learned how to lead without needing to own every line of code. You set direction, you make the hard calls on architecture, and you help engineers work through problems that do not have obvious answers.
You do not wait for perfect clarity. You work with what you have, ask the right questions, align across verification and physical design and firmware, and move the design forward. At Synopsys, you will work on PCIe IP that powers silicon across commercial, enterprise, and automotive customers, and the technical decisions you make will matter.
What You'll Be Doing
• Own the PCIe digital architecture and drive RTL design execution across block, subsystem, and IP integration levels, staying directly involved in design decisions and reviews
• Define micro-architecture, design specifications, and implementation strategies for high-performance, power-efficient, and scalable PCIe IP
• Lead end-to-end digital design activities from architecture definition through RTL development, debug, design convergence, and post-silicon support
• Serve as the technical authority for PCIe design, resolving complex issues and making critical design trade-offs that affect current and next-generation IP
• Mentor ASIC digital design engineers through design reviews, technical feedback, and hands-on problem solving
• Collaborate with verification, physical design, formal, emulation, firmware, and system teams to ensure seamless IP integration and silicon success
• Drive design quality through rigorous reviews, coding standards, and maintainability practices that raise the bar across the team
The Impact You Will Have
• Deliver industry-leading PCIe digital IP that powers silicon for customers building next-generation products across commercial, enterprise, and automotive markets
• Strengthen the technical foundation and execution quality of PCIe designs used by leading semiconductor companies
• Influence the technical strategy and roadmap for Synopsys PCIe and interconnect IP, shaping architecture decisions that affect multiple product generations
• Raise the technical capability of the team through mentorship, design leadership, and knowledge sharing that builds long-term strength
• Improve design predictability, quality, and execution efficiency through strong architectural leadership and disciplined engineering practices
• Drive Synopsys' position as a leader in high-speed interface IP by delivering robust, scalable, and silicon-proven solutions
• Enable faster time-to-market for customers by delivering PCIe IP that integrates cleanly and performs reliably in complex SoC environments
What You'll Need
• Bachelor's degree in Electrical Engineering with 12+ years of ASIC digital design experience, or Master's degree with 10+ years
• Demonstrated experience as a technical lead or principal engineer driving complex ASIC digital design projects
•
Job Title:
• Principal Digital Design Engineer, PCIe
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years deep in the details of PCIe digital design, and somewhere along the way you became the person others come to when a design decision matters or when something complex needs untangling. You know PCIe architecture not just from specs but from living through silicon bring-up, debugging corner cases at 2 a.m., and watching designs either hold up or fall apart under real-world conditions. That experience shaped how you think about micro-architecture, trade-offs, and what actually ships.
You are technical first. You still review RTL. You still care about how a clock domain crossing is handled or whether a state machine will scale to the next generation. But you have also learned how to lead without needing to own every line of code. You set direction, you make the hard calls on architecture, and you help engineers work through problems that do not have obvious answers.
You do not wait for perfect clarity. You work with what you have, ask the right questions, align across verification and physical design and firmware, and move the design forward. At Synopsys, you will work on PCIe IP that powers silicon across commercial, enterprise, and automotive customers, and the technical decisions you make will matter.
What You'll Be Doing
• Own the PCIe digital architecture and drive RTL design execution across block, subsystem, and IP integration levels, staying directly involved in design decisions and reviews
• Define micro-architecture, design specifications, and implementation strategies for high-performance, power-efficient, and scalable PCIe IP
• Lead end-to-end digital design activities from architecture definition through RTL development, debug, design convergence, and post-silicon support
• Serve as the technical authority for PCIe design, resolving complex issues and making critical design trade-offs that affect current and next-generation IP
• Mentor ASIC digital design engineers through design reviews, technical feedback, and hands-on problem solving
• Collaborate with verification, physical design, formal, emulation, firmware, and system teams to ensure seamless IP integration and silicon success
• Drive design quality through rigorous reviews, coding standards, and maintainability practices that raise the bar across the team
The Impact You Will Have
• Deliver industry-leading PCIe digital IP that powers silicon for customers building next-generation products across commercial, enterprise, and automotive markets
• Strengthen the technical foundation and execution quality of PCIe designs used by leading semiconductor companies
• Influence the technical strategy and roadmap for Synopsys PCIe and interconnect IP, shaping architecture decisions that affect multiple product generations
• Raise the technical capability of the team through mentorship, design leadership, and knowledge sharing that builds long-term strength
• Improve design predictability, quality, and execution efficiency through strong architectural leadership and disciplined engineering practices
• Drive Synopsys' position as a leader in high-speed interface IP by delivering robust, scalable, and silicon-proven solutions
• Enable faster time-to-market for customers by delivering PCIe IP that integrates cleanly and performs reliably in complex SoC environments
What You'll Need
• Bachelor's degree in Electrical Engineering with 12+ years of ASIC digital design experience, or Master's degree with 10+ years
• Demonstrated experience as a technical lead or principal engineer driving complex ASIC digital design projects
•
