Powerdomain implementation

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: Power-domain implementation ( Low-power/IR-Drop / Reliability) Engineer – Senior/Staff/Sr. Staff Engineer Location : Bangalore/Hyderabad/Ahmedabad/Noida Experience Level: 3+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Join a development team and execute/lead the power domain implementation for an advanced ASIC/SOCs for a high-profile Silicon Valley start-up. In this highly visible role, as part of a highly talented team you will be at the heart of the ASIC/SOC design effort interfacing with all disciplines with critical impact in getting functional products to of customers quickly. As a Sr, ASIC/SOC Power-domain implementation Engineer, you will be a part of the SOC digital design team responsible for providing integrated solutions into a growth industry Key Qualifications The position requires thorough knowledge of the ASIC design power implementation flow and methodology. • B.Tech/M.Tech/PhD with at least 3+ years hands-on experience in ASIC/SOC low-power implementation/Power-analysis/IR Drop analysis/Reliability(EM/ESD) Analysis. Experience: • Expertise/Experience in one of more areas of Low-power implementation, UPF, IR/EM analysis, Power-analysis, ESD analysis, SIPI/Thermal analysis implementation and methodologies • Power-analysis with a good understanding of low-power implementation techniques – Multi-VT, multi-Voltage, DVFS, multiple power domains • Understanding of UPF and related formats to understand low-power intent, ability to resolve MVRC or low-power check failures • Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs • Power calculation and correlation at different stages from RTL to post-SI • Perform IR Drop and Electromigration analysis at block-level and full-chip level • Perform ESD analysis, Pathfinder checks, Electromigration sign-off • Able to define IR/EM sign-off criterion and implementation • Experience in power-implementation of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 12nm and below. • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and back-end related methodology and tools. Skills: • Experience with one or more tools – MVRC, CLP, VCLP, Redhawk, Voltus, Pathfinder, PERC, PT-PX • Proficient in scripting languages (Tcl and Perl). • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.). • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. Responsibilities Include • Full chip and block level low-power implementation/analysis ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). • Develop and maintain methodology and flows related to low-power implementation, power analysis, and sign-off. • Generation of block and full chip analysis reports and provide fixes • Analyze power analysis reports and utilize scripting techniques to develop insights and drive rapid power sign-off. • Support digital chip integration work and flows. What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more