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Physical Backend Design Engineer
Jobs
#615552
Full Time
Job Description
, or a related field (Master s preferred)
• 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation
• Experience with tape-out of designs for advanced nodes is highly desirable
• Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design
• Experience with physical verification tools like Cadence Pegasus or Mentor Calibre
• Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC)
• Scripting skills in Python, Tcl, Perl, or Shell for automation
• Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite
It would be nice if you also had:
• Experience with advanced process nodes (e.g., 7nm and below)
• Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating
• Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies
• Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets.
• Execute automated place and route (PnR) using industry-standard tools to generate physical layouts.
• Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution.
• Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements.
• Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks.
• Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards.
• Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance.
• Work closely with foundry teams to address process technology issues and implement best practices.
• 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation
• Experience with tape-out of designs for advanced nodes is highly desirable
• Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design
• Experience with physical verification tools like Cadence Pegasus or Mentor Calibre
• Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC)
• Scripting skills in Python, Tcl, Perl, or Shell for automation
• Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite
It would be nice if you also had:
• Experience with advanced process nodes (e.g., 7nm and below)
• Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating
• Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies
• Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets.
• Execute automated place and route (PnR) using industry-standard tools to generate physical layouts.
• Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution.
• Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements.
• Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks.
• Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards.
• Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance.
• Work closely with foundry teams to address process technology issues and implement best practices.
