Minimum 2 years of experience in System Verilog HVL SVA Assertions. Must have executed at least 2 SoC IP Formal Verification signoff projects. Must have used Synopsys VC Formal, Cadence Jasper or Questa Formal Tools comprehensively Hands on experience of developing Formal SV assertion checkers, coverage register, regressions. Functional Checks Assertions based Property coding to verify RTL Structures Data Path, Security, Register, Functional Safety and X Prorogation Verification Connectivity Checks on IP SoC connections Fault Analysis using Formal Test bench Analyzer Formal Coverage and Regressions To enable screen reader support, press +Option+Z To learn about keyboard shortcuts, press slash
