ASIC RTL Design Engineer

Job DetailsAbout CompanyReviewsBenefitsSalaries
Job highlights
5-12 years experience in ASIC RTL design with expertise in Verilog/SystemVerilog and knowledge of AMBA protocols

Develop RTL from specs, perform microarchitecture design, integrate SoC/IP, support synthesis and timing closure, collaborate across teams

5 - 10 Years

2 Vacancies

Not disclosed

Noida, Ahmedabad, Bengaluru
Must have key skills
RTL Design
Other key skills
Spyglass,
CDC,
SOC Design,
Lint,
Verilog,
RTL Coding,
ASIC Design,
Digital Design,
Logic Design
Job description
What you’ll do

ASIC RTL Design Engineer

Experience: 5 to 12 Years
Location: Bangalore | Hyderabad | Pune | Noida | Ahmedabad | Chennai

Role Summary

We are seeking a hands-on ASIC RTL Design Engineer with strong expertise in RTL design and SoC development. The ideal candidate should have experience in designing high-quality, synthesizable RTL for complex ASIC/SoC projects.

Key Responsibilities

Develop RTL using Verilog/SystemVerilog based on architectural specifications.
Perform microarchitecture design, RTL coding, and SoC/IP integration.
Collaborate with Verification, DFT, Physical Design, and Architecture teams.
Support synthesis, lint, CDC, timing closure, and silicon bring-up.
Participate in design reviews and technical discussions.
Required Skills

Strong RTL design experience using Verilog/SystemVerilog.
Good understanding of digital design fundamentals and ASIC design flow.
Experience with synthesis, lint, CDC, and STA concepts.
Knowledge of AMBA protocols (AXI/AHB/APB) is preferred.
Scripting in TCL, Python, Perl, or Shell is an added advantage.

Industry type
Electronic Components / Semiconductors
Department
Engineering - Hardware & Networks
Role
Hardware and Networks - Other
Role category
Hardware and Networks - Other
Employment type
Full Time, Permanent
Education
B.Tech / B.E. in Any Specialization