Senior RTL Design engineers
Senior RTL Design Engineers
Experience : 3-5 years
Location : Hyderabad
Strong RTL(verilog/system verilog) skills with experience in IP development.
• Ability to verify designs by writing simple testbenches.
• Strong foundation in logic synthesis and timing closure concepts.
• Good knowledge of SoC architecture, AXI bus protocols, hardware debug.
• Experience of working with Xilinx FPGAs, Vivado tool flows and micro architecture development is a plus.
Interested,please drop your updated resume to janagaradha.n@acldigital.com
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Experience : 3-5 years
Location : Hyderabad
Strong RTL(verilog/system verilog) skills with experience in IP development.
• Ability to verify designs by writing simple testbenches.
• Strong foundation in logic synthesis and timing closure concepts.
• Good knowledge of SoC architecture, AXI bus protocols, hardware debug.
• Experience of working with Xilinx FPGAs, Vivado tool flows and micro architecture development is a plus.
Interested,please drop your updated resume to janagaradha.n@acldigital.com